1. Field of the Invention
The present invention generally relates to repeated pattern exposure on semiconductor wafers, and more particularly to a process that erases alignment marks as it steps across the wafer so that alignment marks only remain on the edge of the wafer.
2. Description of the Related Art
Semiconductor device fabrication is achieved by lithographical exposures of multiple layers of repeating arrays of circuitry patterns on a wafer. The circuitry patterns of the chips on a wafer are surrounded by non-active regions (kerf regions) that have scribe features used for alignment marks, overlay marks, electrical structures, and other process monitoring structures. In addition to the repeating chip images, scribe features also repeat across the wafer. However, not all scribe features are useful for every single exposure. Inclusion of such non-active features increases the overall die dimension and decreases the number of dies per wafer, which increases unit cost.